Deep Neural Networks (DNN) can perform cognitive tasks such as speech recognition, drug discovery and object detection with high accuracy and efficiency. Training a DNN, however, can be an energy- and time-consuming task. Hardware-based accelerators have the potential to out-perform software implementations. A synaptic element of the DNN can be important in this type of approach.
It has been proposed to utilize a nonvolatile memory with multilevel conductance that can perform a weight update operation by stochastic multiplication as the synaptic element to provide a Resistive Processing Unit (RPU). Such an RPU, may require 1000 levels of conductance with an increase/decrease systematic mismatch below 5%, which may be difficult to accomplish with phase-change memory (PCM) and resistive random access memory (RRAM) due to their fundamental asymmetry.